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| Freescale Semiconductor Mask Set Errata MSE908JB8_3K45H Rev. 1, 8/2006 Mask Set Errata for Mask 3K45H Introduction This mask set errata applies to the mask 3K45H for these products: * MC68HC908JB8 MCU Device Mask Set Identification The mask set is identified by a 5-character code consisting of a version number, a letter, two numerical digits, and a letter, for example 3K45H. All standard devices are marked with a mask set number and a date code. USB Reset Description SE116-USB When the USB module is enabled, the USB reset disable bit (RSTD) in the configuration register (CONFIG) is cleared and a USB reset is detected, there is a small chance the device will fail. (c) Freescale Semiconductor, Inc., 2006. All rights reserved. Workaround When the USB module is enabled and a USB reset is detected, either an internal reset or an interrupt to the CPU can be generated. Which one is generated depends on the RSTD bit of CONFIG. Configuring the USB reset to generate a USB interrupt request to the CPU by setting the RSTD bit of CONFIG fixes this problem. When a USB reset is detected in the interrupt routines, you have two choices: * * Reconfigure the USB module and other related registers Use software to cause a device reset, for example, illegal opcode Example code to implement an illegal opcode: USB_ISR: brclr b_RSTF,UIR1,No_USB_Reset ;check USB reset db $32 ;illegal opcode No_USB_Reset Power-Up from LVR Description SE115-Power A few devices start abnormally during power-up. The issue is the release of the low voltage reset (LVR) earlier than the VREG reaching the CMOS logic operating voltage (typical 0.65 V). The LVR takes the VDD but not the VREG as a reference. LVR exists until the VDD reaches the LVR threshold voltage (VLVR). The problem happens in few devices when the VDD rises quickly and the VREG rises slowly. If the LVR has been released but the VREG doesn't reach the CMOS logic operating voltage, the LVR does not have any effect. This might cause the internal logic to improperly initialize and the MCU might not start normally. Therefore, the VDD voltage must be lower than the VLVR minimum (2.8 V) when the VREG voltage reaches the CMOS logic operating voltage. Workaround To fix the problem, add a 10 series resistor between the power supply and the VDD, and place a 10 F capacitor at the VDD pin and a 4.7 F capacitor at the VREG pin. Mask Set Errata for 908JB8, Mask 3K45H 2 Freescale Semiconductor MCU VDD VSS VREG 0.1 F + 10 VDD 10 F 0.1 F + 4.7 F Glitch on Timer Buffered PWM Output SE30-PWM In timer buffered PWM operation, when a timer overflow (TOF) event or an output compare (OC) event coincides with a write to either pair of the timer channel registers (TCHxH/L), the duty cycle at the PWM output glitches to 0% or 100% momentarily, then returns to proper operation. To avoid the glitches when changing the PWM duty cycle, do not write to either pair of the timer channel registers at the TOF or OC. For example, in the TOF interrupt service routine: If the OC occurs near the last TOF, write to the timer channel registers after the OC; if the OC occurs near the next TOF, write to the timer channel registers before the OC. A write to the channel register high byte (TCHxH) should immediately followed by a write to the low byte (TCHxL) to avoid TOF or OC occurring between the writes. Instruction cycle times must be included when making timing calculations. The figure below shows a typical timer buffered PWM output waveform, indicating the TOF and OC events. Mask Set Errata for 908JB8, Mask 3K45H Freescale Semiconductor 3 TOF OC TOF OC TOF OC TOF TOF OC Timer buffered PWM output Pulse width Period NOTES: Do not write to either pair of timer channel registers at: TOF (timer overflow), or OC (timer output compare) edges. In buffered PWM, the pulse width is defined by the last written pair of timer channel registers. Each pair of timer channel registers consist of a high byte register (TCHxH) and a low byte register (TCHxL). Mask Set Errata for 908JB8, Mask 3K45H 4 Freescale Semiconductor |
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